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IC Tester - S100S50 TEST SYSTEM

IC Tester - S100S50 TEST SYSTEM

Features:
  • 64 to 256 Logic I/O pins, expandable in 64-pin increments
  • Up to 32-site parallel testing — simultaneous testing of up to 32 DUTs
  • Any pin, any resource assignment to any site
  • Logic, Mixed-Signal, and Analog test options
  • Cable-mount solution for flexible system integration
Functions:
Logic & APG Board
  • 50 MHz operation
  • TG and level control per pin, 64 Logic I/O pins
  • 32 Timing Sets and 32 Format Sets with on-the-fly switching
  • 16X, 16Y, 16D Algorithmic Pattern Generation
  • +11V / –2V, 35 mA driving capability
  • 2 DPS, 8 PMU, 64 PPMU, TMU, DVM
  • 17M local memory

Mixed-Signal Board
  • +40V, –15V / ±1.8A V/I Source & Meter ×8
  • 500 KSPS / 16-bit AWG & Digitizer
  • RMS, DVM, TMU, and Data Acquisition Unit
  • 32 User Relays

OPM Board
  • 64 channels, force and sense per channel
  • +40V, –15V / ±1.8A V/I Source & Meter ×8
  • 4 DVM, TMU
  • 32 User Relays


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